3D Package Technology and Assembly Processes 

This PDC provides details on current and future assembly 3D packaging processes and technologies. The 3D IC and wafer-level packaging area is driven by mobile devices data centers, automotive and aerospace. Advanced packaging requirements require the evolution of backend manufacturing to become more process control driven. The 3D stacked die TSV packaging has advantages, but only in some market segments. In the cell phone market, stacking chips helps to minimize some of the interconnect issues between the logic and the memory chips. Fan-out panel level packaging (FOPLP) is moving to stacked die configurations with heterogeneous die integration. Flip chip assembly challenges include copper pillar thermal compression bonding, bump stack material changes, tighter bump pitch, underfill flow and no-flow options, new under fill materials, thermal management with improved thermal interface materials (TIM), embedded passives, and die attach films. Wire bonding remains a key assembly method for 3D memory packages. This workshop will cover 3D and 2.5D (interposer) designs, 3D assembly flow, known good die, KGD, concerns, 3D package testing issues, supply line logistics, thermal management, bump metallization options, wafer thinning and handling (thermal & laser debonding and residue removal) and interposers with microfluidics cooling built-in. The objective of this workshop is to provide the students with an overview of the technologies, materials, and processes involved in the latest 3D and 2.5D assembly processes.