Advanced Assembly Processes of Wafer Level Fan Out Packaging

Dr. Tom Dory

This workshop provides focuses on current and future assembly processes and technologies used in fan out package assembly. The objective of this workshop is to provide the students with an overview of the technologies, materials, and processes involved in the latest fan out package assembly processes. The package end user, designer and sub-cons must compare all package options on the basis of functional attributes including form factor, I/O density, performance & cost to select appropriate package from the many fan out options available. Currently there are several choices for package assembly using fan out wafer level packages (FOWLPs).  The original fan-out package; the embedded wafer-level ball-grid array (eWLB) continues to be popular. At the low cost end are low density fan out packages with <500 IOs with >8 micron L/S. At the high cost end are stacked die packages with >500 IOs and < 8 micron L/S.  Multiple die can now be included in a fan out package incorporating stacked die connected using Through Silicon Vias (TSVs). The workshop provides a detailed comparison of advanced packaging technologies including all varieties of fan out packages including FOWLPs & SiPs to 3D stacked dice interconnected with TSVs. 

Major topics covered in this workshop are:

  1. Fan out wafer level packaging options
  2. Thermal requirements driving package material
  3. Mechanical requirements driving package materials
  4. Wafer Thinning Processes and Handling
    1. The use of a carrier and temporary bonding materials
  5. Wafer carriers or switch to panels? 
  6. Coreless substrate vs. cored substrate assembly
  7. Wafer dicing methods including laser scribing, saw, and plasma
  8. Wire bonded stacked die
  9. Flip chip package options
  10. FOWLP and FOCSP (fan out chip scale package) options
  11. Wire bond assembly
  12. Die attach material selection
  13. Stacked die wire bonding assembly process flow
  14. Silicon interposer design and uses in 2.5D packages
  15. Stacked die packages using TSV
  16. Thermal control in 3D packages
  17. Flip chip bump material options
  18. Thermal reflow and thermal compression bonding
  19. Package material selection to meet end user requirements
  20. Summary and review

Who Should Attend?

  • Manufacturing engineers and technicians, 
  • Manufacturing supervisors
  • Production and quality control engineers
  • Front of the line packaging engineers and technicians
  • Operations management, planning and support personnel