Flip Chip Package Technology and Assembly Processes

Dr. Tom Dory

Course Description: The objective of this PDC is to provide an improved understanding of current flip chip package options and assembly flows. This PDC will begin with a discussion of current flip chip assembly including fanout wafer level packaging (FOWLP) and 2.5 & 3D package assembly. We will then discuss the newer technology options and issues. Flip chip packaging assembly is not new, but newer device requirements require more connections between the die and package, a tighter bump pitch and more functionally in the package. Laptop computers, tablets and smart phones, using flip chip packaging with thinned die and thin packages are driving new assembly requirements.  All new technology drivers bring new challenges that will be discussed in this PDC. These assembly challenges include copper pillar bonding, bump stack material changes, tighter bump pitch, underfill flow and no-flow options, new under fill materials, thermal management with improved thermal interface materials (TIM), embedded passives, and die attach films. Also discussed are current wafer thinning process options including bonding and debonding to a carrier. Dicing and handling thin wafers and die will be covered. Newer bump materials will be discussed with their impact to flip chip or stacked die package assembly. 

Main Topics:

  1. A review of package designs and market drivers
    1. Major flip chip package types including wafer level package, WLP, multichip packaging, MCP, and system on chip, SoC
    2. Single chip and multiple chip package designs
  2. Semiconductor roadmaps for Assembly
    1. Smaller packages for mobile applications and larger packages for more functionally
  3. Introduction to package assembly processes
    1. HVM flip chip assembly process flows
  4. Major classes of bumps including electroplated, solder paste and stud bumps
  5. Wafer thinning and handling methods
  6. Wafer saw and dicing processes
    1. Laser dicing, plasma dicing and different saw blade types
  7. Die bond/die attach processes using different die attach materials and reflow processes
  8. Flip chip solder joint reliability
    1. Failure modes and ways to avoid them
  9. Underfill process options including no-flow underfill
    1. Underfill material selection
  10. Wafer level packaging processes
  11. Embedded passive devices in the substrate
  12. Cutting edge package technology including 3D packaging and TSV process options
    1. Technology drivers for 3D packages
    2. Die stacking options in 3D packages including chip to chip and chip to wafer
  13. Summary and review

Who Should Attend?

  • Assembly manufacturing engineers and technicians
  • Process engineers
  • Assembly integration engineers
  • Material science engineers
  • Equipment support technicians 
  • Technical marketing engineers with some technical background