Principal Semiconductor and IC Packaging Consultant
Dr. Dory has extensive experience in microelectronics covering semiconductor fab processing and assembly, hybrid circuits, and package assembly & test. Dr. Dory retired from Intel Corporation in the Assembly He is a senior member of IEEE.
and Test Technology Development Research division after 20 years in R&D.
He was a member of the Arizona State University chemical engineering faculty with a focus on mass transport and fab processing.
As Pathfinding Integration Manager of the Intel Substrate Technology Research Labs, he was responsible for development of advanced packaging technology in the areas of MEMS including wafer level bonding, stacked die packages, and line pitch reduction designs. He specializes in packaging and assembly, focusing on high density substrate manufacturing, and chip assembly including flip chip and stacked die and 3D packaging. He was awarded ten patents while at Intel in the areas of embedded package capacitors, underfill applications, and package design.
As the Fujifilm Electronic Materials R&D manager for formulated products was co-author on 15 patents in the area of semiconductor selective etchants and cleaners.
He has taught numerous workshops and presented technical papers in both fab technology and semiconductor assembly processes in both the U.S., China, Malaysia and Europe.
His areas of expertise include:
· Wirebond package assembly
· Flipchip package assembly
· Failure analysis in package assembly
· Wafer level fan out advanced assembly options
· 3D package assembly process options
· Package assembly process optimization
Additional areas of expertise in the science of fab processing include:
· Science of semiconductor fab wet and dry etch science
· Semiconductor fab deposition processes
· Rapid thermal processing, RTP, control
· Through silicon via, TSV, science and process options
· Metallization methods including PVD, ALD and CVD